As is known to those in semiconductor device manufacturing, interconnect delay is a limiting factor in the drive to improve the speed and performance of integrated circuits (IC). One way to minimize interconnect delay is to reduce interconnect capacitance by using low dielectric constant (low-k) materials and ultra-low-k dielectric materials in metal interconnects during back-end-of-line (BEOL) operations for IC production. Such low-k materials presently include organosilicates, such as organosilicon glass or SiCOH-containing materials.
Thus, in recent years, low-k materials have been developed to replace relatively high dielectric constant insulating materials, such as silicon dioxide. In particular, low-k materials are being utilized for inter-level and intra-level dielectric layers between metal layers of semiconductor devices. Additionally, in order to further reduce the dielectric constant of insulating materials, material films are formed with pores, i.e., porous low-k dielectric materials. Such low-k materials can be deposited by a spin-on dielectric (SOD) method similar to the application of photoresist, or by chemical vapor deposition (CVD). Hence, the use of low-k materials is readily adaptable to existing semiconductor manufacturing processes.
When preparing a new interconnect level on a semiconductor substrate, a cap layer is typically formed overlying the preceding interconnect layer, followed by the formation of the low-k insulation layer and one or more layers, such as a hard mask, overlying the low-k insulation layer. Upon formation of the insulation stack, lithography and etch processing are used to pattern the insulation layers in preparation for subsequent metallization processes. For example, the insulation layer stack may be patterned with a trench-via structure according to various integration schemes, including dual damascene integration, when preparing a metal line and contact plug to provide electrical continuity between one interconnect layer and an adjacent interconnect layer.
However, the practical implementation of low-k materials in insulation layer stacks for metal interconnects faces formidable challenges. Ultimately, it is desirable to integrate low-k dielectric materials in metal interconnects that achieve the full benefit of the reduced dielectric constant, while producing a structurally robust, patterned insulation layer with minimal damage.
When Cu is used as a metallic interconnect, a Physical Vapor Deposition (PVD) barrier layer must be employed to prevent copper diffusion into surrounding materials (which would degrade their properties). The PVD barrier must be continuously and evenly applied to eventually receive Cu electroplating that is free of voids and defects. It has been observed that undercuts (wherein the trench width of a higher elevation layer is more narrow than a lower level layer) between the dielectric hard mask layer and underlying low-k insulation layer impair Cu metallization.
While wet hard mask removal may produce acceptable etching results, it requires a separate tool in addition to the dry reactive ion etch (RIE) tool used for damascene and dual damascene pattern etching. There is thus a need for an improved dry etch method for profiling a film stack while maintaining a high degree of uniformity between layers that form trench-vias.